HMS30C7110 Datasheet, PDF (136/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Register Address R/W Description
Reset value
INTPND 0x10
R/W 0 = The interrupt has not been requested
0x00000000
1 = The interrupt source has asserted a request
Each field and the corresponding bit position are the same as those of SRCPND register.
2.12.1.6. INTERRUPT OFFSET REGISTER (INTOFS, offset = 0x14)
If INTPND[n] is set to 1 (due to interrupt requests from sources), number “n” is shown in this
register. This is for the ease of an interrupt target address computation, i.e., target address =
INTOFS << 2.
Note that the valid value of this register is 0 – 31 when an interrupt occurs. If it is 32, it means that
there happens no interrupts, i.e., INTPND = 0.
Table 2.102 Interrupt Offset Register
Address : 1930_0014
Register Address R/W Description
Reset value
INTOFS 0x14
R
“n” in 0 – 31 if INTPND[n] is set to 1.
0x00000020
32 if there happens no interrupt.
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
136
Version 1.5