HMS30C7110 Datasheet, PDF (46/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

2.3. Clock/Watchdog Timer
HMS30C7110
The HMS30C7110® integrates a clock module, which is composed of the clock generator, the reset
de-bouncing circuit, and watchdog timer (WDT). The clock generator provides the system clock.
The main PLL multiplies the incoming external crystal clock input by 7(default). Assuming 10 MHz
external clock is used and 70MHz of the CPU speed is intended, the register setting is to be
“multiplying by 7”. An internal register also provides a method to determine the ratio between CPU
clock and bus clock. It can be either 1:1 or 2:1. To run CPU with maximum performance, set the
PLL output frequency to 70MHz and set the ratio to 1:1, then CPU runs in 70MHz and all others
run at 70 MHz.
Watchdog Timer generates the reset signal internally when the timer reaches the end value. So, the
controlling software must reload the preset value to the timer before the timer expires during normal
operation. Complete descriptions of these registers are given in the Register Section.
2.3.1. Block Diagram
The Clock Module consists of several blocks such as a register file, a reset de-bouncer, a clock
generator, and a watchdog timer.
system clock
Clock
Generator
DLL
Register
File
( slave )
Peripheral bus
Reset
Debounce
RESET_IN
HRESETn
Figure 2.1 Block Diagram of Clock Module
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