HMS30C7110 Datasheet, PDF (57/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

2.5. Memory Controller (SDRAM)
HMS30C7110
The HMS30C7110® integrates a SDRAM controller (SDRAMC) that supports a 32-bit SDRAM
array. EDO or FPM type DRAM is not supported. The operating clock is directly related to the
internal system bus speed. When the system bus clock runs at 70MHz, the SDRAMC runs at
70MHz. When the system bus clock runs at 35MHz, the SDRAMC runs at 35MHz. The system
clock can be selected by PLL output clock or half of PLL output clock. The SDRAMC is fully
configurable through a set of control register. Complete descriptions of these registers are given in
the Register Section. The operating clock of SDRAMC is shown on SCLK.
Note: SDRAM space works either in 32-bit wide or in 16-bit wide. So, any design using the
SDRAM space as program memory space, it can be either 32-bit wide memory structure or
16-bit wide structure. Being used as data memory space, SDRAM may be connected to 8-bit
wide data bus sacrificing the address corresponding to unconnected data bus.
The thirteen multiplexed address lines, MA[12:0], and two bank select signals, A13 and A14, allow
the HMS30C7110® to support 1M, 2M, 4M, 8M, 16M and 32M×32 bit arrays or 1M, 2M, 4M, 8M,
16M, 32M and 64M×16 bit arrays. Both symmetric (Number of row addresses and number of
column addresses are same) and asymmetric addressing (Number of row addresses and number of
column addresses are different) is supported. The HMS30C7110® has one nSCS pin. The
maximum block size is 128Mbytes. For write operations of less than word in size, the
HMS30C7110® supports byte-wise write. The HMS30C7110® provides refresh functionality with
programmable rate (normally SDRAM refresh rate is 1 / 64ms).
2.5.1. Block Diagram
The SDRAM controller of HMS30C7110® consists of several blocks such as main state machine,
register file, refresh block, data-path, signal generator and address generator.
Commands come in via system bus will be interpreted in the main state machine and the main state
machine controls all of the signal generation blocks (address generator, signal generator and data-
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