HMS30C7110 Datasheet, PDF (83/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

5:0 RO 0x0 The number of RX_BSTAT available for read
HMS30C7110
2.6.2.11. RX_ADDR_RETURN (offset = 0x28)
This read only register provides RX address used.
Table 2.33 RX Address Return
Bits Access Default Description
31:0 RO 0x00 RX address return
MAC0 Address : 1920_0028
MAC1 Address : 1920_1028
2.6.2.12. CTRL_MODE (offset = 0x2C)
This register defines two operation modes: Rx preamble and control frames. For transmit pause
frame format, refer to P_FRM_ADDR_0, P_FRM_ADDR_1, P_FRM_ID, and P_FRM_VALUE
starting at address offset 0x90.
Table 2.34 Control Mode Register Bit Definition
MAC0 Address : 1920_002C
MAC1 Address : 1920_102C
Bits Access Default Description
31:24 RW 0
Reserved
23:20 RW 0
Reserved
19:16 RW 0
Minimum number of valid preambles for a valid RX frame
0 = No preamble byte: when SFD found, it is considered as a valid frame
1 = One preamble byte is required to be considered as a valid frame.
…
7 = Seven preamble bytes are required to be considered as a valid frame.
Set to 0 for RMII mode.
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