HMS30C7110 Datasheet, PDF (17/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

1.3. Pin Assignments
HMS30C7110
Pin #
1
Pin Name
MODE
2
TESTSE
3
nRESET
4
VSSP
5
MCLK
6
SCLK
7
VSSI
8
ADDR21/Endian
9
ADDR20/Boot32
10
ADDR19/Boot16-8
11
ADDR18/Bypass
Table 1.1 PQFP Pin List
IO
Pad
Description
Type
I
PICD Operation Mode
MODE TESTSE
Contents
0
0
Normal Operation
0
1
NANDTREE/BIST/PLL Test
1
0
Parallel Capture for ATPG
1
1
Scan Shift for ATPG
I
PICD Test Scan Enable. Refer to the description for Pin 1
I
PICS System Reset, active low
P
VSS for IO
I
PICS SDRAM Memory Feedback Clock
O
POC8A SDRAM clock
P
VSS for core
BD PBCD8A Address Bus/Endian at Reset period. . Pulled down internally over 50 Kohm.
0: Little Endian (Default)
1: Big Endian
BD PBCD8A Address Bus/Boot32 at Reset period. Pulled down internally over 50 Kohm.
0: 16-bit booting(Default)
1: 32-bit booting
BU PBCU8A Address Bus/Boot16-8 at Reset. Pulled up internally over 50 Kohm.
0: 8-bit booting
1: 16-bit booting(Default)
BU PBCU8A Address Bus/Bypass Internal Power-On-Reset Circuit. Pulled up internally over
50 Kohm. The active output width is over 1.5 Sec when 10MHz main clock is
used.
0: Use internal Power-On-Reset ciruit
1: Bypass internal Power-On-Reset circuit (Default)
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Version 1.5