HMS30C7110 Datasheet, PDF (87/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
Table 2.37 MII Transmit Data Register
Bits Access Default Description
31:16
0
Reserved
15:0 RW 0
Data to be written to the PHY
MAC0 Address : 1920_0038
MAC1 Address : 1920_1038
2.6.2.16. MII_RXDATA (offset = 0x3C)
The CPU can read contents of registers from PHY by issuing read command via MII_CMD register.
Table 2.38 MII Receive Data Register
Bits Access Default Description
31:16
0
Reserved
15:0 RW 0
Data received from PHY
MAC0 Address : 1920_003C
MAC1 Address : 1920_103C
2.6.2.17. LENGTH (offset = 0x44)
This register defines upper and lower bound of payload length of a MAC frame. It also defines
maximum burst transfer length between Ethernet MAC and system memory.
Table 2.39 Length Register
MAC0 Address : 1920_0044
MAC1 Address : 1920_1044
Bits Access Default Description
31:16 RW 0x05dc Maximum payload length, default = 1500 in decimal
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