HMS30C7110 Datasheet, PDF (48/161 Pages) List of Unclassifed Manufacturers – Multipurpose Network Processor

HMS30C7110
0
RW 0x0
Main PLL enable
When this bit is set to logic 1, internal CPU and system clock is made
from PLL output. If this is set to logic 0, the internal CPU and system
clock is made directly from external clock pin. The system clock is same
to the Bus Clock or System Bus Clock.
2.3.2.2. Watch Dog Timer (WDT) Control
The Watch Dog control register selects the operation mode of watchdog timer.
Table 2.9 Watch Dog Timer control
Bits Access Default Description
31:5
0x00 Reserved
4
RW 0x0
Enable
0 = Watch dog timer disable
1 = Watch dog timer enable
3:2
0x0 Reserved
1: 0 RW 0x0 Pre-scaler
00 = System Bus Clock
01 = System Bus Clock/ 4
10 = System Bus Clock/ 8
11 = System Bus Clock/ 256
Address : 1830_0004
2.3.2.3. Watch Dog Timer (WDT) Interval
This register contains the watchdog timer interval value. The input clock is the output clock of the
pre-scaler described in Watch Dog Timer (WDT) Control
Table 2.10 Watch Dog Timer Interval
© 2003 MagnaChip Semiconductor Ltd. All Rights Reserved
48
Address : 1830_0008
Version 1.5