SMJ320C80 Datasheet, PDF (96/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
r1
r2
r3
r6
c1
c2
r1
5
Cycle Type
PAC Idle
Row
Tap Point
0 for Full Transfer, 1 for Split Transfer
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 75. Nonpipelined 1-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
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