SMJ320C80 Datasheet, PDF (76/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
Col A
Col B
Col C
Col D
r1
r2
r3
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
RL
A[31:0]
Row
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
r6
col
col
col
col
col
col
r1
c1
c2
c3
c1
c2
c3
c1
c2
c3
c1
c2
c3
PAC PAC PAC PAC
Idle
Col A Col B Col C Col D
–/A
A/B B/C C/D D/–
A
B
C
D
0 For Normal Reads, 1 For PDPT Reads
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
–/A
A/B B/C C/D D/–
Figure 58. Pipelined 1-Cycle/Column Read-Cycle Timing
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