SMJ320C80 Datasheet, PDF (27/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP cache architecture
The MP contains two four-way set-associative, 4K caches for instructions and data. Each cache is divided into
four sets with four blocks in each set. Each block represents 256 bytes of contiguous instructions or data and
is aligned to a 256-byte address boundary. Each block is partitioned into four sub-blocks that each contain
sixteen 32-bit words and are aligned to 64-byte boundaries within the block. Cache misses cause one sub-block
to be loaded into cache. Figure 18 shows the cache architecture for one of the four sets in each cache. Figure 19
shows how addresses map into the cache using the cache tags and address bits.
Block 0
Block 1
Block 2
Block 3
Set 0
Tag Reg 0 (Block 0)
Tag Reg 1 (Block 1)
Tag Reg 2 (Block 2)
Tag Reg 3 (Block 3)
LRU in SET 0
NLRU in SET 0
NMRU in SET 0
MRU in SET 0
LRU Stack for SET 0
LRU
NLRU
NMRU
MRU
Least-recently-used
Next least-recently-used
Next most-recently-used
Most-recently-used
Figure 18. MP Cache Architecture (x4 Sets)
32-Bit Logical Address
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
T T T T T T T T T T T T T T T T T T T T T T S S s s WWWWB B
On-Chip MP 4K Cache RAMS
Bank 0
Bank 1
Set 0
Set 1
Set 2
Set 3
11 10 9 8 7 6 5 4 3 2 1 0
S S A A s s WWWW B B
Address in On-Chip
Cache Bank
T – Tag Address Bits
S – Set Select Bits (0–3)
s – Sub-Block (within block) Select (0–3)
W – Word (within sub-block) Select (0–15)
B – Byte (within word) Select (0–3)
A – Block Select (which tag matched) (0–3)
Figure 19. MP Cache Addressing
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