SMJ320C80 Datasheet, PDF (135/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: cycle completion inputs (see Figure 112 and Figure 113)
The cycle completion inputs are sampled at the beginning of each row access at the start of the r3 state. The
READY input is sampled also at the start of the r6 state and during each column access (2 and 3 cyc/col
accesses only). The RETRY input is sampled on each CLKOUT falling edge following r3. The value n as used
in the parameters represents the integral number of half cycles between the transitions of the two signals in
question.
NO
17 ta(MIDV-CMPV)
18 tsu(CMPV-CKOL)
19 th(CKOL-CMPV)
20 ta(RASL-RRV)
21 ta(RLL-RRV)
22 ta(CASL-RRV)
Access time, RETRY, READY, FAULT valid after memory identification
(A, STATUS) valid
Setup time, RETRY, READY, FAULT valid to CLKOUT no longer high
Hold time, RETRY, READY, FAULT valid after CLKOUT low
Access time RETRY, READY valid from RAS low
Access time, RETRY, READY valid from RL low
Access time, READY valid from CAS low
2 cyc/col accesses
3 cyc/col accesses
MIN
MAX UNIT
ntH–8 ns
7.5
ns
1.2
ns
ntH–7.5 ns
ntH–7.5 ns
tH–12
ns
2tH–8
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