SMJ320C80 Datasheet, PDF (82/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
State
Col A
Col B
Col C
r1 r2 r3 r5
r6 rspin col col col col^† col ci^‡ col col r1
c1 c2
c1 c2 c2
c1 c2
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
6
Cycle Type
Row
PAC
Col A
A
PAC
Idle
Col B
B
A
B
0 For Normal Write, 1 For PDPT Write
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† _{Wait state inserted by external logic (example)}
‡ _{Internally generated pipeline bubble (example)}
A
B
Figure 64. 2-Cycle/Column Write-Cycle Timing
PAC
Col C
C
C
C
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