SMJ320C80 Datasheet, PDF (142/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
external interrupt timing (see Figure 117)
The following description defines the timing of the edge-triggered interrupts EINT1 – EINT3 and the
level-triggered interrupt LINT4 (see Note 4).
NO
MIN
48 tw(EINL)
Pulse duration, EINTx low
6*
49 tsu(EINH-CKOH) Setup time, EINTx high before CLKOUT no longer low
9.5^†
50 tw(EINH)
Pulse duration, EINTx high
6*
51 tsu(LINL-CKOL) Setup time, LINT4 low before CLKOUT no longer high
9.5^†
† _{This parameter must only be met to ensure that the interrupt is recognized on the indicated cycle.}
* This parameter is not production tested.
NOTE 4: In order to ensure recognition, LINT4 must remain low until cleared by the interrupt service routine.
Interrupt Recognized
MAX
UNIT
ns
ns
ns
ns
CLKOUT
EINTx
LINT4
49
50
51
48
Figure 117. External Interrupt Timing
142
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