SMJ320C80 Datasheet, PDF (94/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles
Read-transfer (memory-to-register) cycles transfer a row from the VRAM memory array into the VRAM shift
register (sequential-access memory, or SAM). This causes the entire SAM (both halves of the split SAM) to be
loaded with the array data.
Split-register read-transfer (memory-to-split-register) cycles also transfer data from a row in the memory array
to the SAM. However, these transfers cause only half of the SAM to be written. Split-register read transfers allow
the inactive half of the SAM to be loaded with the new data while the other active half continues to shift data
in or out.
Write-transfer (register-to-memory) cycles transfer data from the SAM into a row of the VRAM array. This
transfer causes the entire SAM (both halves of the split SAM) to be written into the array.
Split-register write-transfer (split-register-to-memory) cycles also transfer data from the SAM to a row in the
memory array. However, these transfers write only half of the SAM into the array. Split-register write transfers
allow the inactive half of the SAM to be transferred into memory while the other (active) half continues to shift
serial data in or out.
Read and split-read transfers resemble a standard read cycle. Write and split-write transfers resemble a
standard write cycle. The TRG/CAS output is driven low prior to the fall of RAS to indicate a transfer cycle. Only
a single column access is performed so RETRY, while required to be at a valid level, has no effect if asserted
at column time. The value output on A[31:0] at column time represents the SAM tap point.
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