SMJ320C80 Datasheet, PDF (92/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
State
r1 r2 r3 r5
Col A
Col B
Col C
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
RL
A[31:0]
Row
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
r6 rspin col col col col^† col ci^‡ col col r1
c1 c2
c1 c2 c2
c1 c2
PAC
Col A
A
PAC
Idle
PAC
Col B
B
Col C
C
Col Sel A
Col Sel B
Col Sel C
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† _{Wait state inserted by external logic (example)}
‡ _{Internally generated pipeline bubble (example)}
A
B
C
Figure 72. 2-Cycle/Column Block-Write-Cycle Timing
92
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