SMJ320C80 Datasheet, PDF (44/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP data-unit architecture
The data unit has independent data paths for the ALU and the multiplier, each with its own set of hardware
functions. The multiplier data path includes a 16 × 16 multiplier, a halfword swapper, and rounding hardware.
The ALU data path includes a 32-bit three-input ALU, a barrel rotator, mask generator, multiple flag (mf)
expander, left/rightmost one and left/rightmost bit-change logic, and several multiplexers. Figure 37 shows the
data-unit block diagram.
dst2 src3
src1/src2/dstc/0
src4
src4/src2 0 src1/0x1
d0
mf
dst/dst1
Rotate Amount
Multiplexer
Barrel Rotator
Mask Generator
Multiplexer
LMO, RMO,
LMBC, RMBC
Expander
Mask
Generator
Multiplier
(Splittable)
Scale
Round
Swap/Merge
C Port
Multiplexer
A
B
C
Three-Input ALU (Splittable)
Barrel
Rotator Input
Sign Bit
ALU
Function
Code Logic
N, C, V, Z, LV mf
src1 Any register, D reg only for left/right most one (LMO/RMO), left/right most bit change (LMBC/RMBC) hardware
scr2 D reg or sometimes 5/32-bit immediate
dst2 D reg only
scr3 D reg only
dstc D reg only (destination companion reg source)
scr4 D reg only
0x1 Constant
dst/dst1 Any register
0 Constant
d0 5 LSBs of d0
Figure 37. Data-Unit Block Diagram
44
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443