SMJ320C80 Datasheet, PDF (133/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
device reset timing requirements (see Figure 110)
NO
9 tw(RSTL)
10 tsu(HRQL-RSTH)
11 th(RSTH-HRQL)
12 tsu(UTML-RSTH)
13 th(RSTH-UTML)
Pulse duration, RESET low
Initial reset during power-up
Reset during active operation
Setup time of HREQ low to RESET high to configure self-bootstrap mode
Hold time, HREQ low after RESET high to configure self-bootstrap mode
Setup time of UTIME low to RESET high to configure big-endian operation
Hold time, UTIME low after RESET high to configure big-endian operation
MIN MAX UNIT
6th
ns
6th
ns
4th
ns
0
ns
4th
ns
0
ns
9
RESET
10
11
HREQ
UTIME
13
12
Figure 110. Device-Reset Timing
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