SMJ320C80 Datasheet, PDF (115/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM write cycles
Write cycles begin with an activate (ACTV) command to activate the bank and select the row. The TC outputs
the column address and activates the TRG/CAS and W strobes for each write command. For burst-length 1
accesses, a write command can occur on each cycle. For burst-length 2 accesses, a write command can occur
every two cycles. The TC drives data out on D[63:0] during each cycle of an active-write command and indicates
valid bytes by driving the appropriate CAS/DQM strobes low. During peripheral device packet transfers, DBEN
remains high and D[63:0] are placed in the high-impedance state so that the peripheral can drive data into the
memories.
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