SMJ320C80 Datasheet, PDF (42/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
communication (comm) register
The comm register contains the packet-transfer handshake bits and PP indicator bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H S Q P – – – – – – – – – – – – – – – – – – – – – – – – – PP#
H High-priority packet transfer
S Packet-transfer suspend
Q Packet transfer queued
P Submit packet transfer request
PP# PP Number (read only)
000 – PP0 010 – PP2
001 – PP1 011 – PP3
1xx – Not implemented
Figure 32. comm Register
cache-tag registers
The tag0 – tag3 registers contain the tag address and sub-block present bits for each cache block.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23-Bit Tag Address
P P P P – – – LRU
P
LRU
Present bit
Least-recently-used code
00 – Most-recently-used (MRU)
10 – next LRU
01 – next MRU (NMRU)
11 – LRU
Sub-Block # 3 2 1 0
Figure 33. Cache-Tag Registers
PP cache architecture
Each PP has its own 2K-byte instruction cache. Each cache is divided into four blocks and each block is divided
into four sub-blocks containing 16 64-bit instructions each. Cache misses cause one sub-block to be loaded
into cache. Figure 34 shows the cache architecture for one of the four sets in each cache. Figure 35 shows how
addresses map into the cache using the cache tags and address bits.
Block 0
Block 1
Block 2
Block 3
Tag 0 (Block 0)
Tag 1 (Block 1)
Tag 2 (Block 2)
Tag 3 (Block 3)
LRU
NLRU
NMRU
MRU
LRU Stack
Figure 34. PP Cache Architecture
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
23-Bit Tag Value
87
sub
6 543
instruction
210
ignored
sub – sub-block
Figure 35. PP Register Cache-Address Mapping
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