SMJ320C80 Datasheet, PDF (144/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
host-interface timing (see Figure 120)
NO
56 tsu(REQV-CKOH) Setup time, REQ1–REQ0 valid to CLKOUT no longer low
57 th(CKOH-REQV) Hold time, REQ1–REQ0 valid after CLKOUT high
58 th(HRQL-HAKL) Hold time for HACK high after HREQ goes low*
59 td(HAKL-OUTZ) Delay time, HACK low to output hi-Z
All signals except D[63:0]
D[63:0]
60 td(HRQH-HAKH)
61 td(HAKH-OUTD)
Delay time, HREQ high to HACK no longer low
Delay time, HACK high to outputs driven^†
62 tsu(HRQL-CKOH) Setup time, HREQ low to CLKOUT no longer low (see Note 5)
* This parameter is not production tested.
NOTE 5: Parameter must be met only to ensure HREQ recognition during the indicated clock cycle.
’C80-40
MIN
MAX
tH – 7
tH – 7
4tH – 12*
1*
1*
10
6tH
8.5
UNIT
ns
ns
ns
ns
ns
ns
CLKOUT
HREQ Sampled
56
57
REQ[1:0]
HREQ
HACK
A[31:0]
RL, TRG,
WE, DSF,
DSF2, DBEN
RAS
CAS[7:0]
D[63:0]
DDIN
62
58
59
60
61
Figure 120. Host-Interface Timing
144
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