SMJ320C80 Datasheet, PDF (147/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
video interface timing: external sync inputs (see Figure 123)
When configured as inputs, the HSYNCn, VSYNCn, and CSYNCn signals may be driven asynchronously. The
following parameters apply only when the inputs are being generated synchronous to FCLKn in order to ensure
recognition on a particular FLCKn edge.
NO
75 tsu(SIL-FCKH) Setup time, HSYNC, VSYNC, or CSYNC low to FCLK no longer low^†
76 th(FCKH-SIL) Hold time, HSYNC, VSYNC, or CSYNC high after FCLK high^‡
77 tsu(SIH-FCKH) Setup time, HSYNC, VSYNC, or CSYNC high to FCLK no longer low^§
78 th(FCKH-SIH) Hold time, HSYNC, VSYNC, or CSYNC low after FCLK high^¶
† _{This parameter must be met only to ensure the input is recognized as low at FLCK edge B.}
‡ _{This parameter must be met only to ensure the input is recognized as high at FLCK edge A.}
§ _{This parameter must be met only to ensure the input is recognized as high at FLCK edge D.}
¶ _{This parameter must be met only to ensure the input is recognized as low at FLCK edge C.}
MIN MAX UNIT
5
ns
7
ns
5
ns
7
ns
FCLK0
FCLK1
HSYNC0, HSYNC1
VSYNC0, VSYNC1
CSYNC0, CSYNC1
(Inputs)
A
B
76
75
C
D
77
78
Figure 123. Video Interface Timing: External Sync Inputs
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