SMJ320C80 Datasheet, PDF (93/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
State
Col A
Col B
Col C
r1 r2 r3 r4 r5 r6 col col col col col col col^† ci^‡ col col col r1
c1 c2 c3
c1 c2 c3 c3
c1 c2 c3
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle
PAC
RL
† _{Wait state inserted by external logic (example)}
‡ _{Internally generated pipeline bubble (example)}
Figure 73. 3-Cycle/Column Block-Write-Cycle Timing
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