SMJ320C80 Datasheet, PDF (119/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM block-write cycles
Block-write cycles allow SVRAMs and SGRAMs to write a stored color value to multiple column locations in a
single access. Block-write cycles are similar to write cycles except that DSF is driven high to indicate a
block-write command. Because burst is not supported for block-write, burst-length 2 accesses generate a single
block-write every other clock cycle.
State
r1
r2
r3
r5
r6 rspin
col
col
col
col
col
col
r1
Col Pipe
Col A
c1
Col B
c1
Col C
c1
Col D
c1
CLKOUT
CT[2:0]
0,1
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC PAC PAC PAC Idle DCAB
RL
A[31:0]
Row
Col A Col B Col C
Col D
RAS
CAS/DQM[7:0]
A
B
C
D
DSF
TRG/CAS
A
B
C
D
W
D[63:0]
Sel A Sel B Sel C Sel D
DBEN
DDIN
Command
ACTV
BLKW BLKW BLKW BLKW
Figure 96. SDRAM Burst-Length 1 Block-Write Cycle Timing
DCAB
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
119