SMJ320C80 Datasheet, PDF (108/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM type cycles (continued)
CASā/āDQM A B C
Col A c1 c2 c3
Col B
c1 c2 c3
Col C
c1 c2 c3
Idle
ci ci ci
Burst-length 1, 2-cycle latency reads, read
transfers, split-read transfers
CASā/āDQM
āA B C
Col A c1 c2 c3 c4
Col B
c1 c2 c3 c4
Col C
c1 c2 c3 c4
Idle
ci ci ci ci
Burst-length 1, 3-cycle latency reads, read
transfers, split-read transfers
CASā/āDQM A āB C
Col A c1
Col B
c1
Col C
c1
Idle
ci
CASā/āDQM A ā(B) C (D) E ā(F)
Col A, B c1 c2 c3
---
Col C, D
c1 c2 c3
---
Col E, F
c1 c2 c3
---
Idle
ci ci ci
Burst-length 1 writes, block writes, SRSs, write transfers,
split-write transfers
Burst-length 2, 2-cycle latency reads, read transfers,
split-read transfers
CASā/āDQM A ā(B) C (D) E ā(F)
CASā/āDQM A ā(B) C (D) E ā(F)
Col A, B c1 c2 c3 c4
Col A, B c1 c2
----
--
Col C, D
c1 c2 c3 c4
Col C, D
c1 c2
----
--
Col E, F
c1 c2 c3 c4
Col E, F
c1 c2
----
--
Idle
ci ci ci ci
Idle
ci ci
Burst-length 2, 3-cycle latency reads, read transfers,
split-read transfers
Burst-length 2, 3-cycle latency writes
CASā/āDQM A ā B
Cā
Col A c1
-
Col B
c1
-
Col C
c1
-
Idle
ci
Burst-length 2, 3-cycle latency block-writes, write
transfers, split-write transfers
Figure 85. SDRAM Column Pipelines
special SDRAM cycles
To initialize the SDRAM properly, the SMJ320C80 performs two special SDRAM cycles after reset. The ’C80
first performs a deactivate cycle on all banks (DCAB) and then initializes the SDRAM mode register with a mode
register set (MRS) cycle. The CT code input at the start of the MRS cycle determines the burst length and latency
that is programmed into the SDRAM mode register.
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