SMJ320C80 Datasheet, PDF (75/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles
Read cycles transfer data or instructions from external memory to the ’C80. The cycles can occur as a result
of a packet transfer, cache request, or DEA request. During the cycle, W is held high, TRG/CAS is driven low
after RAS to enable memory output drivers and DBEN and DDIN are low so that data transceivers can drive
into the ’C80. During column time, the TC places D[63:0] into the high-impedance state, allowing it to be driven
by the memory and latches input data during the appropriate column state. The TC always reads 64 bits and
extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. During
peripheral device packet transfers, DBEN and DDIN remain high.
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