SMJ320C80 Datasheet, PDF (126/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles (continued)
State
Col Pipe
r1
r2
r3
r5
r6
col
col
col
col
r1
c1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
01x
Cycle Type
Row
PAC
Idle
DCAB
Tap Pt.
0 For Full, 1 For Split
ACTV
WTR
DCAB
Figure 103. SVRAM Burst-Length 2, Write-Transfer Cycle Timing
SDRAM refresh cycle
The SDRAM refresh cycle is performed when the TC receives an SDRAM cycle timing input (CT=0xx) at the
start of a refresh cycle. The RAS and TRG/CAS outputs are driven low for one cycle to strobe a refresh
command (REFR) into the SDRAM. The refresh address is generated internal to the SDRAM. The ’C80 outputs
a 16-bit pseudo-address (used for refresh bank decode) on A[31:16] and drives A[15:0] low.
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