SMJ320C80 Datasheet, PDF (12/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions (Continued)
TERMINAL
NAME
TYPE^†
DESCRIPTION
HOST INTERFACE
HACK
Host acknowledge. The ’C80 drives HACK output low following an active HREQ to indicate that it has driven
O
the local memory bus signals to the high-impedance state and is relinquishing the bus. HACK is driven high
asynchronously following HREQ being detected inactive, and then the ’C80 resumes driving the bus.
HREQ
Host request. An external device drives HREQ low to request ownership of the local memory bus. When
HREQ is high, the ’C80 owns and drives the bus. HREQ is synchronized internally to the ’C80’s internal
I
clock. Also, HREQ is used at reset to determine the power-up state of the MP. If HREQ is low at the rising
edge of RESET, the MP comes up running. If HREQ is high, the MP remains halted until the first interrupt
occurrence on EINT3.
REQ1, REQ0
Internal cycle request. REQ1 and REQ0 provide a two-bit code indicating the highest-priority memory cycle
O
request that is being received by the TC. External logic can monitor REQ1 and REQ0 to determine if it is
necessary to relinquish the local memory bus to the ’C80.
SYSTEM CONTROL
CLKIN
I
Input clock. CLKIN generates the internal ’C80 clocks to which all processor functions (except the frame
timers) are synchronous.
CLKOUT
Local output clock. CLKOUT provides a way to synchronize external circuitry to internal timings. All ’C80
O
output signals (except the VC signals) are synchronous to this clock.
EINT1, EINT2, EINT3
Edge-triggered interrupts. EINT1, EINT2 and EINT3 allow external devices to interrupt the master
processor (MP) on one of three interrupt levels (EINT1 is the highest priority). The interrupts are rising-edge
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triggered. EINT3 also serves as an unhalt signal. If the MP is powered-up halted, the first rising edge on
EINT3 causes the MP to unhalt and fetch its reset vector (the EINT3 interrupt-pending bit is not set in this
case).
LINT4
Level-triggered interrupt. LINT4 provides an active-low level-triggered interrupt to the MP. Its priority falls
I
below that of the edge-triggered interrupts. Any interrupt request should remain low until it is recognized
by the ’C80.
RESET
Reset. RESET is driven low to reset the ’C80 (all processors). During reset, all internal registers are set
I
to their initial state and all outputs are driven to their inactive or high-impedance levels. During the rising
edge of RESET, the MP reset mode and the ’C80’s operating endian mode are determined by the levels
of HREQ and UTIME pins, respectively.
XPT2–XPT0
I
External packet transfer. XPT2–XPT0 are used by external devices to request a high-priority XPT by the
TC.
EMULATION CONTROL
EMU0, EMU1^‡
I/O
Emulation pins. EMU0 and EMU1 are used to support emulation host interrupts, special functions targeted
at a single processor, and multiprocessor halt-event communications.
TCK^‡
TDI^‡
I
Test clock. TCK provides the clock for the ’C80 IEEE-1149.1 logic, allowing it to be compatible with other
IEEE-1149.1 devices, controllers, and test equipment designed for different clock rates.
I
Test data input. TDI provides input data for all IEEE-1149.1 instructions and data scans of the ’C80.
TDO
TMS^‡
O
Test data output. TDO provides output data for all IEEE-1149.1 instructions and data scans of the ’C80.
I
Test-mode select. TMS controls the IEEE-1149.1 state machine.
TRST^§
I
Test reset. TRST resets the ’C80 IEEE-1149.1 module. When low, all boundary-scan logic is disabled,
allowing normal ’C80 operation.
† _{I = input, O = output, Z = high-impedance}
‡ _{This pin has an internal pullup and can be left unconnected during normal operation.}
§ _{This pin has an internal pulldown and can be left unconnected during normal operation.}
¶ _{For proper operation, all VDD and VSS pins must be connected externally.}
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