SMJ320C80 Datasheet, PDF (21/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP double-precision floating-point accumulators
There are four double-precision floating-point registers (see Figure 8) to accumulate intermediate floating-point
results.
63
a0
a1
a2
a3
MSB
Accumulator 0
Accumulator 1
Accumulator 2
Accumulator 3
0
LSB
S Sign bit
E Exponent
M Value
MS Most significant
LS Least signficant
Figure 8. Double-Precision Floating-Point Accumulators
MP control registers
In addition to the general-purpose registers, there are a number of control registers that are used to represent
the state of the processor. Table 1 shows the control register numbers of the accessible registers.
Table 1. Control Register Numbers
NUMBER
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
NAME
EPC
EIP
CONFIG
—
INTPEN
—
IE
—
FPST
—
PPERROR
—
—
PKTREQ
TCOUNT
TSCALE
FLTOP
FLTADR
FLTTAG
FLTDTL
FLTDTH
DESCRIPTION
Exception Program Counter
Exception Instruction Pointer
Configuration
Reserved
Interrupt Pending Register
Reserved
Interrupt Enable Register
Reserved
Floating-Point Status
Reserved
PP Error Register
Reserved
Reserved
Packet-Transfer Request
Register
Current Counter Value
Counter Reload Value
Faulting Operation
Faulting Address
Faulting Tag
Faulting Data (low)
Faulting Data (high)
NUMBER
0x0015–0x001F
0x0020
0x0021
0x0022–0x002F
0x0030
0x0031
0x0032
0x0033
0x0034
0x0035–0x0038
0x0039
0x003A
0x003B–0x01FF
0x0200 – 0x020F
0x0300
0x0400–0x040F
0x0500
0x4000
0x4001
0x4002
NAME
—
SYSSTK
SYSTMP
—
MPC
MIP
—
ECOMCNTL
ANASTAT
—
BRK1
BRK2
—
DESCRIPTION
Reserved
System Stack Pointer
System Temporary Register
Reserved
Emulator Exception Program Counter
Emulator Exception Instruction Pointer
Reserved
Emulator Communication Control
Emulation Analysis Status Register
Reserved
Emulation Breakpoint 1 Register
Emulation Breakpoint 2 Register
Reserved
iCACHET Instruction Cache Tags 0 to 15
iCACHEL
dCACHET
dCACHEL
IN0P
IN1P
OUTP
Instruction Cache LRU Register
Data Cache Tags 0 to 15
Data Cache LRU Register
Vector Load Pointer 0
Vector Load Pointer 1
Vector Store Pointer
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