SMJ320C80 Datasheet, PDF (114/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM read cycles (continued)
State
r1
r2
r3
Col Pipe
CLKOUT
CT[2:0]
3
r5
r6
col
col
col
col
col
col
r1
Col A
c1
c2
c3
c4
Col B
c1
c2
c3
c4
Col C
c1
c2
c3
c4
Col D
c1
c2
c3
c4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle DCAB
RL
A[31:0]
Row
Col A (Col B) Col C
(Col D)
RAS
CAS/DQM[7:0]
A
B
C
D
DSF
TRG/CAS
A, B
C, D
W
D[63:0]
A
B
C
D
DBEN
0 For Normal Read, 1 For PDPT Read
DDIN
Command
ACTV
READ
READ
DCAB
Figure 91. SDRAM Burst-Length 2, 3-Cycle Latency Read-Cycle Timing
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