SMJ320C80 Datasheet, PDF (34/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 7. Summary of MP Opcodes
INSTRUCTION
add
and.tt
and.ff
and.ft
and.tf
bbo
bbz
bcnd
br
brcr
bsr
cmnd
cmp
dcache
estop
fadd
fcmp
fdiv
DESCRIPTION
Signed integer add
Bitwise AND
Bitwise AND with 1s complement
Bitwise AND with 1s complement
Bitwise AND with 1s complement
Branch bit one
Branch bit zero
Branch conditional
Branch always
Branch control register
Branch and save return
Send command
Integer compare
Flush data cache sub-block
Emulation stop
Floating-point add
Floating-point compare
Floating-point divide
fmpy
Floating-point multiply
frndx
Floating-point convert/round
fsqrt
Floating-point square root
fsub
Floating-point subtract
illop
Illegal operation
jsr
Jump and save return
ld
Load signed into register
ld.u
Load unsigned into register
lmo
Leftmost one
or.tt
Bitwise OR
INSTRUCTION
or.ff
or.ft
or.tf
rdcr
rmo
shift.dz
shift.dm
shift.ds
shift.ez
shift.em
shift.es
shift.iz
shift.im
st
sub
swcr
trap
vadd
vmac
vmpy
vmsc
vmsub
vrnd(FP)
vrnd(Int)
vsub
xnor
xor
DESCRIPTION
Bitwise OR with 1s complement
Bitwise OR with 1s complement
Bitwise OR with 1s complement
Read control register
Rightmost one
Shift, disable mask, zero extend
Shift, disable mask, merge
Shift, disable mask, sign extend
Shift, enable mask, zero extend
Shift, enable mask, merge
Shift, enable mask, sign extend
Shift, invert mask, zero extend
Shift, invert mask, merge
Store register into memory
Signed integer subtract
Swap control register
Trap
Vector floating-point add
Vector floating-point multiply and add to
accumulator
Vector floating-point multiply
Vector floating-point multiply and subtract
from accumulator
Vector floating-point subtract accumulator
from source
Vector round with floating-point input
Vector round with integer input
Vector floating-point subtract
Bitwise exclusive NOR
Bitwise exclusive OR
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