SMJ320C80 Datasheet, PDF (124/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles (continued)
State
Col Pipe
r1
r2
r3
r5
r6
col
col
col
col
r1
c1
c2
c3
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
011
Cycle Type
PAC
Idle
DCAB
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
Row
Tap Pt.
0 For Full, 1 For Split
ACTV
RTR
DCAB
Figure 101. SVRAM Burst-Length 2, 3-Cycle Latency Read-Transfer Cycle Timing
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