SMJ320C80 Datasheet, PDF (41/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
pipeline registers (continued)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pc
PC (29-Bit Doubleword Address)
–GL
G – Global Interrupt Enable
L – Loop Inhibit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ipa
32-Bit Copy of the Previous pc Register Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ipe
32-Bit Copy of the Previous ipa Register Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
iprs
29-Bit Doubleword Return Address
–––
Figure 30. Pipeline Registers
interrupt registers
The interrupt-enable (inten) register allows individual interrupts to be enabled and configures the interrupt flag
(intflg) register operation. The intflg register contains the interrupt flag bits. Interrupt priority increases moving
from left to right on intflg.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
inten r r r r E E E E – – – E E E E – – E – – – – – – – – – – – – – W
PPPP
PPPP
3210
MMMM
SSSS
GGGG
MP P P
T
PTTT
A
ME EQ
S
SNR
K
GDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
intflg r r r r I I I I – – – I I I I – – I – – – – – – – – – – – – – –
r
E
W
PPnMSG
Reserved (write as 0)
Enable interrupt
Write mode
0 – writing 1 clears intflg
1 – writing 1 sets intflg
PPn message interrupt
MPMSG
PTEND
PTERR
PTQ
TASK
MP message interrupt
Packet transfer complete
Packet-transfer error
Packet transfer queued
MP task interrupt
Figure 31. PP-Interrupt Registers
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