SMJ320C80 Datasheet, PDF (56/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP opcode formats (continued)
Table 15 shows the encoding used in the opcodes to specify particular PP registers. A 3-bit register field
contains the three least significant bits (LSBs). The register codes are used for the src, src1, src2, src3, src4,
dst, dst1, dst2, d, reg, Ga, La, Gim/X, and Lim/X opcode fields. The four most significant bits (MSBs) specify
the register bank which is concatenated to the register field for the full 7-bit code. The register bank codes are
used for the dstbank, s1bnk, srcbank, 0bank, bank, Adstbank, and As1bank opcode fields. When no associated
bank is specified for a register field in the opcode, the D register bank is assumed. When the MSB of the bank
code is not specified in the opcode (as in 0bank and s1bnk), it is assumed to be 0, indicating a lower register.
Table 15. PP Register Codes
LOWER REGISTERS (MSB OF BANK = 0)
CODING
CODING
REGISTER
REGISTER
BANK REG
BANK REG
0000 000
a0
0100 000
d0
0000 001
a1
0100 001
d1
0000 010
a2
0100 010
d2
0000 011
a3
0100 011
d3
0000 100
a4
0100 100
d4
0000 101 reserved
0100 101
d5
0000 110
a6 (sp)
0100 110
d6
0000 111 a7 (zero)
0100 111
d7
0001 000
a8
0101 000 reserved
0001 001
a9
0101 001
sr
0001 010
a10
0101 010
mf
0001 011
a11
0101 011 reserved
0001 100
a12
0101 100 reserved
0001 101 reserved
0101 101 reserved
0001 110 a14 (sp)
0101 110 reserved
0001 111 a15 (zero) 0101 111 reserved
0010 000
x0
0110 000 reserved
0010 001
x1
0110 001 reserved
0010 010
x2
0110 010 reserved
0010 011 reserved
0110 011 reserved
0010 100 reserved
0110 100 reserved
0010 101 reserved
0110 101 reserved
0010 110 reserved
0110 110 reserved
0010 111 reserved
0110 111 reserved
0011 000
x8
0111 000
pc/call
0011 001
x9
0011 010
x10
0111 001
0111 010
ipa/br
ipe ^†
0011 011 reserved
0111 011
iprs
0011 100 reserved
0111 100
inten
0011 101 reserved
0111 101
intflg
0011 110 reserved
0111 110
comm
0011 111 reserved
0111 111
lctl
† _{Read only}
UPPER REGISTERS (MSB OF BANK = 1)
CODING
CODING
REGISTER
REGISTER
BANK REG
BANK REG
1000 000 reserved
1100 000
lc0
1000 001 reserved
1100 001
lc1
1000 010 reserved
1100 010
lc2
1000 011 reserved
1100 011 reserved
1000 100 reserved
1100 100
lr0
1000 101 reserved
1100 101
lr1
1000 110 reserved
1100 110
lr2
1000 111 reserved
1100 111 reserved
1001 000 reserved
1101 000
lrse0
1001 001 reserved
1101 001
lrse1
1001 010 reserved
1101 010
lrse2
1001 011 reserved
1101 011 reserved
1001 100 reserved
1101 100
lrs0
1001 101 reserved
1101 101
lrs1
1001 110 reserved
1101 110
lrs2
1001 111 reserved
1101 111 reserved
1010 000 reserved
1110 000
ls0
1010 001 reserved
1110 001
ls1
1010 010 reserved
1110 010
ls2
1010 011 reserved
1110 011 reserved
1010 100 reserved
1110 100
le0
1010 101 reserved
1110 101
le1
1010 110 reserved
1110 110
le2
1010 111 reserved
1110 111 reserved
1011 000 reserved
1111 000 reserved
1011 001 reserved
1111 001 reserved
1011 010 reserved
1111 010 reserved
1011 011
1011 100
1011 101
1011 110
1011 111
reserved
reserved
reserved
reserved
reserved
1111 011
1111 100
1111 101
1111 110
1111 111
reserved
tag0 ^†
tag1 ^†
tag2 ^†
tag3 ^†
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