SMJ320C80 Datasheet, PDF (31/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
MP opcode summary (continued)
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Table 4. Short-Immediate Opcodes
3322 2222222211 1111111100000000 00
1098 7654321098 7654321098765432 10
illop0
Dest
Source
0000000
Unsigned Immediate
trap – – – – E – – – – – 0 0 0 0 0 0 1
Unsigned Trap Number
cmnd – – – – – – – – – – 0 0 0 0 0 1 0
Unsigned Immediate
rdcr
Dest
–––––0000100
Unsigned Control Register Number
swcr
Dest
Source
0000101
Unsigned Control Register Number
brcr – – – – – – – – – – 0 0 0 0 1 1 0
Unsigned Control Register Number
shift.dz
Dest
Source
0001000––– i n
Endmask
Rotate
shift.dm
Dest
Source
0001001––– i n
Endmask
Rotate
shift.ds
Dest
Source
0001010––– i n
Endmask
Rotate
shift.ez
Dest
Source
0001011––– i n
Endmask
Rotate
shift.em
Dest
Source
0001100––– i n
Endmask
Rotate
shift.es
Dest
Source
0001101––– i n
Endmask
Rotate
shift.iz
Dest
Source
0001110––– i n
Endmask
Rotate
shift.im
Dest
Source
0001111––– i n
Endmask
Rotate
and.tt
Dest
Source2
0010001
Unsigned Immediate
and.tf
Dest
Source2
0010010
Unsigned Immediate
and.ft
Dest
Source2
0010100
Unsigned Immediate
xor
Dest
Source2
0010110
Unsigned Immediate
or.tt
Dest
Source2
0010111
Unsigned Immediate
and.ff
Dest
Source2
0011000
Unsigned Immediate
xnor
Dest
Source2
0011001
Unsigned Immediate
or.tf
Dest
Source2
0011011
Unsigned Immediate
or.ft
Dest
Source2
0011101
Unsigned Immediate
or.ff
Dest
Source2
0011110
Unsigned Immediate
ld
Dest
Base
0 1 0 0 M SZ
Signed Offset
ld.u
Dest
Base
0 1 0 1 M SZ
Signed Offset
st
Source
Base
0 1 1 0 M SZ
Signed Offset
dcache – – – – F
Source2
0 1 1 1 M0 0
Signed Offset
bsr
Link
–––––100000A
Signed Offset
jsr
Link
Base
100010A
Signed Offset
bbz
BITNUM
Source
100100A
Signed Offset
bbo
BITNUM
Source
100101A
Signed Offset
bcnd
Cond
Source
100110A
Signed Offset
cmp
Dest
Source2
1011000
Signed Immediate
add
Dest
Source2
1 0 1 1 0 0U
Signed Immediate
sub
Dest
Source2
1 0 1 1 0 1U
Signed Immediate
– Reserved bit (code as 0)
A Annul delay slot instruction if branch taken
E Emulation trap bit
F Clear present flags
i Invert endmask
M Modify, write modified address back to register
n Rotate sense for shifting
SZ Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword)
U Unsigned form
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