SMJ320C80 Datasheet, PDF (61/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
relative-addressing mode codes
The Lrm and Grm opcode fields allow the local-address or global-address units, respectively, to select
PP-relative addressing as shown in Table 25.
Table 25. Relative-Addressing Mode Codes
CODING
RELATIVE-ADDRESSING
MODE
00
Normal (absolute addressing)
01
Reserved
10
PP-relative dba
11
PP-relative pba
Legend:
dba – Data RAM 0 base is base address
pba – Paramater RAM base is base address
condition codes
In the four conditional parallel transfer opcodes (formats 7–10), the condition code field specifies one of
16 condition codes to be applied to the data unit operation source, data unit result, or global transfer based on
the settings of the c, r, and g bits, respectively. Table 26 shows the condition codes. For the 32-bit immediate
data unit opcode (format D), the condition applies to the data unit result only. See Figure 45 for PP opcode
formats.
Table 26. Condition Codes
CONDITION
BITS
35 34 33 32
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MNEMONIC
u
p
ls
hi
lt
le
ge
gt
hs, c
lo, nc
eq, z
ne, nz
v
nv
n
nn
DESCRIPTION
Unconditional (default)
Positive
Lower than or same
Higher than
Less than
Less than or equal
Greater than or equal
Greater than
Higher than or same, carry
Lower than, no carry
Equal, zero
Not equal, not zero
Overflow
No overflow
Negative
Nonnegative
STATUS BIT COMBINATION
None
~N & ~Z
~C | Z
C & ~Z
(N & ~V) | (~N & V)
(N & ~V) | (~N & V) | Z
(N & V) | (~N & ~V)
(N & V & ~Z) | (~N & ~V & ~Z)
C
~C
Z
~Z
V
~V
N
~N
EALU operations
Extended ALU (EALU) operations allow the execution of more advanced ALU functions than those specified
in the base set ALU opcodes. The opcode for EALU instructions contains the operands for the operation while
the d0 register extends the opcode by specifying the EALU operation to be performed. The format of d0 for EALU
operations is shown in Figure 24.
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