SMJ320C80 Datasheet, PDF (71/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write support
The SMJ320C80 supports three modes of VRAM block-write. The block-write mode is dynamically selectable
so that software can specify block-writes regardless of the type of block-write the addressed memory supports.
Block-writes are supported only for 64-bit buses. During block-write and load-color-register cycles, the BS[1:0]
inputs determine which block mode will be used.
Table 34. Block-Write Selection
BS[1:0]
00
01
10
11
BLOCK-WRITE MODE
Simulated
Reserved
4x
8x
SDRAM support
The SMJ320C80 provides direct support for synchronous DRAM (SDRAM), synchronous VRAM (SVRAM), and
synchronous graphics RAM (SGRAM). During ’C80 power-up refresh cycles, the external system must signal
the presence of these memories by inputting a CT2 value of 0. This causes the ’C80 to perform special
deactivate (DCAB) and mode register set (MRS) commands to initialize the synchronous RAMs. Figure 54
shows the MRS value generated by the ’C80.
SDRAM Mode
Register Bit 11 10 9 8 7 6 5 4 3 2
0 0 0 0 0 0 1 CT0 0 0
CT0, CT1 as input at the start of the MRS cycle
10
0 CT1
Figure 54. MRS Value
Because the MRS register is programmed through the SDRAM address inputs, the alignment of the MRS data
to the ’C80 logical-address bits is adjusted for the bus size (see Figure 55). The appearance of the MRS bits
on the ’C80 physical-address bus is dependent on the address multiplexing as selected by the AS[2:0] inputs.
’C80 LOGICAL ADDRESS BITS
BS[1:0] A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00
X X X X 11 10 9 8 7 6 5 4 3 2 1 0
01
X X X 11 10 9 8 7 6 5 4 3 2 1 0 X
10
X X 11 10 9 8 7 6 5 4 3 2 1 0 X X
11
X 11 10 9 8 7 6 5 4 3 2 1 0 X X X
Figure 55. MRS Value Alignment
memory cycles
SMJ320C80 external memory cycles are generated by the TC’s external memory controller. The controller’s
state machine generates a sequence of states which define the transition of the memory interface signals. The
state sequence is dependent on the cycle timing selected for the memory access being performed as shown
in Figure 56. Memory cycles consist of row states and the column pipeline.
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