SMJ320C80 Datasheet, PDF (22/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP pipeline registers
The MP uses a three-stage fetch, execute, access (FEA) pipeline. The primary pipeline registers are
manipulated implicitly by branch and trap instructions and are not accessible by the user. The exception and
emulation pipeline registers are user-accessible as control registers. All pipeline registers are 32 bits.
Program Counter
Instruction Pointer
Instruction Register
Normal
PC
IP
IR
Program Execution Mode
Exception
EPC
EIP
Emulation
MPC
MIP
• Instruction register (IR) contains the instruction being
executed.
• Instruction pointer (IP) points to the instruction being
executed.
• Program counter (PC) points to the instruction being
fetched.
• Exception/emulator instruction pointer (EIP/MIP) points to the
instruction that would have been executed had the exception /
emulation trap not occurred.
• Exception/emulator program counter (EPC/MPC) points to the
instruction to be fetched on returning from the exception/emulation
trap.
Figure 9. MP FEA Pipeline Registers
configuration (CONFIG) register (0x0002)
The CONFIG register controls or reflects the state of certain options as shown in Figure 10.
3322222222221111111111
10987654321098765432109876 ⁵⁴³²¹⁰
ERTHX
Reserved
Type
Reserved
Release
Reserved
E
R
T
H
X
Type
Release
Endian mode; 0 = big-endian, 1 = little-endian, read only
PPData RAM round robin; 0 = fixed, 1 = variable, read/write
TC packet transfer (PT) round robin; 0 = variable, 1 = fixed, read/write
High priority MP events; 0 = disabled, 1 = enabled, read/write
Externally initiated packet transfers; 0 = disabled, 1 = enabled, read/write
Number of PPs in device, read only
SMJ320C80 version number
Figure 10. CONFIG Register
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