SMJ320C80 Datasheet, PDF (110/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
special SDRAM cycles (continued)
State
r1
CLKOUT
r2
r3
r5
r1
CT[2:0]
0xx
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Figure 87. SDRAM Mode-Register-Set Cycle Timing
SDRAM read cycles
Read cycles begin with an activate (ACTV) command to activate the bank and to select the row. The TC outputs
the column address and activates the TRG/CAS strobe for each read command. For burst-length 1 accesses,
a read command can occur on each cycle. For burst-length 2 accesses, a read command can occur every two
cycles. The TC places D[63:0] into the high-impedance state, allowing it to be driven by the memory, and latches
input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the
appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. The CAS/DQM strobes are
activated two cycles before input data is latched. If the second column in a burst is not required, then CAS/DQM
is not activated. During peripheral device packet transfers, DBEN remains high.
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