SMJ320C80 Datasheet, PDF (103/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
refresh cycles
Refresh cycles are generated by the TC at the programmed refresh interval. They are characterized by the
following signal activity:
D CAS falls prior to RAS.
D All CAS pins (CAS[7:0]) are active.
D TRG, W, and DBEN all remain inactive (high) because no data transfer occurs.
D DSF is active (high) at the fall of CAS and is driven inactive prior to the fall of RAS.
D The data bus is driven to the high-impedance state.
D The upper half of the address bus (A[31:16]) contains the refresh pseudo-address and the lower half
(A[15:0]) is driven to all zeros.
D If RETRY is asserted at any sample point during the cycle, the cycle timing is not modified. Instead, the
pseudo-address and backlog counters are simply not decremented.
D Selecting user-modified timing has no effect on the cycles.
D Upon completion of the refresh cycle, the memory interface returns to state r1 to await the next access.
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