SMJ320C80 Datasheet, PDF (80/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
State
r1
r2
r3
Col A
Col B
Col C
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
r6 rspin rspin ^{col col}
ci^{† col} drn
r1
c1
c1
c1
RETRY
STATUS[5:0]
Cycle Type
PAC PAC Idle PAC Drain
RL
A[31:0]
Row
Col A Col B
Col C
RAS
CAS/DQM[7:0]
DSF
A
B
C
TRG/CAS
W
D[63:0]
DBEN
DDIN
A
B
C
0 For Normal Write, 1 For PDPT Write
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† _{Internally generated pipeline bubble (example)}
A
B
C
Figure 62. Pipelined 1-Cycle/Column Write-Cycle Timing
80
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