SMJ320C80 Datasheet, PDF (70/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
cycle time selection
The ’C80 supports eight basic sets of memory timings to support various memory types directly. The cycle timing
is selected by the value input on the CT[2:0] pins at row time. The selected timing remains in effect until the next
row access.
CT[2:0]
000
001
010
011
100
101
110
111
Table 32. Cycle-Timing Selection
MEMORY TIMING
Pipelined (Burst Length 1) SDRAM, CAS Latency of 2
Pipelined (Burst Length 1) SDRAM, CAS Latency of 3
Interleaved (Burst Length 2) SDRAM, CAS Latency of 2
Interleaved (Burst Length 2) SDRAM, CAS Latency of 3
Pipelined 1 Cycle/Column
Nonpipelined 1 Cycle/Column
2 Cycle/Column
3 Cycle/Column
page sizing
Whenever an external memory access occurs, the TC records the 22 most significant bits of the address in its
internal LASTPAGE register. The address of each subsequent (column) access is compared to this value. The
page size value input on the PS[3:0] pins determines which bits of LASTPAGE are used for this comparison.
If a difference exists between the enabled LASTPAGE bits and the corresponding bits of the next access, then
the page has changed and the next memory access begins with a new row-address cycle.
Table 33. Page-Size Selection
PS[3:0]
ADDRESS BITS COMPARED
PAGE SIZE (BYTES)
0000
A[31:6]
64
0001
A[31:7]
128
0010
A[31:8]
256
0011
A[31:9]
512
0100
A[31:10]
1K
0101
A[31:18]
256K
0110
A[31:19]
512K
0111
1000
A[31:20]
A[31:0]
1M
1–8^†
1001
A[31:11]
2K
1010
A[31:12]
4K
1011
A[31:13]
8K
1100
A[31:14]
16K
1101
A[31:15]
32K
1110
A[31:16]
64K
1111
A[31:17]
128K
† _{PS[3:0] = 1000 disables page-mode cycles so that the effective page size is the same}
as the bus size
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