SMJ320C80 Datasheet, PDF (148/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
emulator interface connection
The ’C80 supports emulation through a dedicated emulation port that is a superset of the IEEE Standard 1149.1
(JTAG) Standard. To support the ’C80 emulator, a target system must include a 14-pin header (2 rows of 7 pins)
with the connections shown in Figure 124. Table 38 describes the emulation signal.
TMS ₁
TDI ₃
PD(+3.3V) ₅
TDO ₇
TCKRET ₉
TCK ₁₁
EMU0 ₁₃
2 ^TRST
4 ^GND
6 ^{No pin (key)}
8 ^GND
10 ^GND
12 ^GND
14 ^EMU1
Pin Spacing: 0.100 in. (X,Y)
Pin Width: 0.025 in, square post
Pin Length: 0.235 in. nominal
(see Table 38)
Figure 124. Target System Header
Table 38. Target Connectors
XDS510
SIGNAL
TMS
TDI
TDO
TCK
TRST
EMU0
EMU1
PD (3.3 V)
XDS510
STATE
O
O
I
O
O
I
I
I
TARGET
STATE
I
I
O
I
I
I/O
I/O
O
DESCRIPTION
Test-mode select^†
Test-data input^†
Test-data output^†
Test clock – 10-MHz clock source from emulator. Can be used to drive system-test clock.^†
Test reset^†
Emulation pin 0
Emulation pin 1
Presence detect. Indicates that the target is connected and powered up. Should be tied to
+ 3.3 V on target system.
TCKRET
I
† _{IEEE Standard 1149.1}
O
Test clock return. Test clock input to the XDS510 emulator. Can be buffered or unbuffered
version of TCK.^†
For best results, the emulation header should be located as close as possible to the ’C80. If the distance exceeds
six inches, the emulation signals should be buffered. See Figure 125.
XDS510 is a trademark of Texas Instruments Incorporated.
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