SMJ320C80 Datasheet, PDF (132/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
general notes on timing parameters
The period of the output clock (CLKOUT) is twice the period of the input clock (CLKIN), or 2 × t_c(CKI). The half
cycle time (t_H) that appears in the following tables is one-half of the output clock period, or equal to the input
clock period, t_c(CKI).
All output signals from the ’C80 (including CLKOUT) are derived from an internal clock such that all output
transitions for a given half cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
CLKIN timing requirements (see Figure 108)
NO
1 tc(CKI)
Period of CLKIN (tH)
2 tw(CKIH) Pulse duration of CLKIN high
3 tw(CKIL) Pulse duration of CLKIN low
4 tt(CKI)
Transition time of CLKIN
* This parameter is not production tested.
MIN MAX
10
4.2
4.2
1.5*
UNIT
ns
ns
ns
ns
CLKIN
1
2
3
4
4
Figure 108. CLKIN Timing
local-bus switching characteristics over full operating range: CLKOUT^† (see Figure 109)
NO
PARAMETER
MIN
MAX UNIT
5 tc(CKO) Period of CLKOUT
2tc(CKI)^‡*
ns
6 tw(CKOH) Pulse duration of CLKOUT high
tH–4.5
ns
7 tw(CKOL) Pulse duration of CLKOUT low
tH–4.5
ns
8 tt(CKO)
Transition time of CLKOUT
2.5* ns
† _{The CLKOUT output has twice the period of CLKIN. No propagation delay or phase relationship to CLKIN is ensured. Each state of a memory}
access begins on the falling edge of CLKOUT.
‡ _{This parameter can also be specified as 2tH.}
* This parameter is not production tested.
tH
tH
5
6
tH
tH
8
8
CLKOUT
7
Figure 109. CLKOUT Timing
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