SMJ320C80 Datasheet, PDF (64/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
TC functional block diagram (continued)
Src MUX and
Alignment
64
Crossbar
Interface
Src
Controller
Src Control
Registers
Packet Transfer
FIFO
Cache Buffer
64
64
Cache, VRAM, and
Refresh Controller
Dst MUX and
Alignment
Dst
Controller
Dst Control
Registers
External
Memory
64
Interface
Memory
Configuration
Cache
Request Queuing and Prioritization
Figure 46. TC Block Diagram
TC registers
The TC contains four on-chip memory-mapped registers accessible by the MP.
refresh control (REFCNTL) register (0x01820000)
The REFCNTL register controls refresh cycles.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPARLD
REFRATE
RPARLD Refresh Pseudo-Address Reload Value
REFRATE Refresh Interval (in clock cycles)
Figure 47. REFCNTL Register
packet-transfer minimum (PTMIN) register (0x01820004)
The PTMIN register determines the minimum number of cycles that a packet transfer executes before being
suspended by a higher priority packet transfer.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMIN
Figure 48. PTMIN Register
64
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