SMJ320C80 Datasheet, PDF (146/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
video interface timing: FCLK input and video outputs (see Note 6 and Figure 122)
NO
MIN MAX UNIT
67 tc(FCK)
FCLK period
25
ns
68 tw(FCKH)
Pulse duration, FCLK high
8
ns
69 tw(FCKL)
Pulse duration, FCLK low
8
ns
70 tt(FCK)
Transition time, FCLK (rise and fall)
2* ns
71
th(FCKL-SYL)
Hold time, HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK, or CAREA high after FCLK
low
0
ns
72
th(FCKL-SYH)
Hold time, HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK, or CAREA low after FCLK
low
0
ns
73
td(FCKL-SYL)
Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK,
or CAREA low
20 ns
Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK,
74 td(FCKL-SYH) _{or CAREA high}
20 ns
* This parameter is not production tested.
NOTE 6: Under certain circumstances, these outputs also can transition asynchronously. These transitions occur when controller timing register
values are modified by user programming. If the new register value forces the output to change states, then this transition occurs without
regard to FCLK inputs.
70
68
67
70
69
FCLK0
FCLK1
HSYNCn, VSYNCn,
CSYNCn/HBLNKn
CBLNKn/VBLNKn
CAREAn
74
73
72
71
Figure 122. Video Interface Timing: FCLK Input and Video Outputs
146
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