SMJ320C80 Datasheet, PDF (17/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
master processor (MP) architecture
The master processor (MP) is a 32-bit RISC processor with an integral IEEE-754 floating-point unit. The MP
is designed for effective execution of C code and is capable of performing at well over 130000 dhrystones/s.
Major tasks which the MP typically performs are:
D Task control and user interface
D Information processing and analysis
D IEEE-754 floating point (including graphics transforms)
MP functional block diagram
Figure 3 shows a block diagram of the master processor. Key features of the MP include:
D 32-bit RISC processor
– Load/store architecture
– Three operand arithmetic and logical instructions
D 4K-byte instruction cache and 4K-byte data cache
– Four-way set associative
– Least-recently-used (LRU) information replacement
– Data writeback
D 4K-byte noncached parameter RAM
D Thirty-one 32-bit general-purpose registers
D Register and accumulator scoreboard
D 15-bit or 32-bit immediate constants
D 32-bit byte addressing
D Scalable timer
D Leftmost-one and rightmost-one logic
D IEEE-754 floating-point hardware
– Four double-precision floating-point vector accumulators
– Vector floating-point instructions
Floating-point operation and parallel load or store
Multiply and accumulate
D High performance
– 50 million instructions per second (MIPS)
– 100 million floating-point operations per second (MFLOPS)
– Over 130000 dhrystones/s
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