SMJ320C80 Datasheet, PDF (68/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
local memory interface (continued)
Table 30. Column-Time Status Codes
STATUS[5:0]
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
CYCLE TYPE
PP0 Low-Priority Packet Transfer
PP0 High-Priority Packet Transfer
PP0 Instruction Cache
PP0 DEA
PP1 Low-Priority Packet Transfer
PP1 High-Priority Packet Transfer
PP1 Instruction Cache
PP1 DEA
PP2 Low-Priority Packet Transfer
PP2 High-Priority Packet Transfer
PP2 Instruction Cache
PP2 DEA
PP3 Low-Priority Packet Transfer
PP3 High-Priority Packet Transfer
PP3 Instruction Cache
PP3 DEA
MP Low-Priority Packet Transfer
MP High-Priority Packet Transfer
MP Urgent Packet Transfer (Low)
MP Urgent Packet Transfer (High)
XPT/VCPT in Progress
XPT/VCPT Complete
MP Instruction Cache (Low)
MP Instruction Cache (High)
MP DEA (Low)
MP DEA (High)
MP Data Cache (Low)
MP Data Cache (High)
Frame 0
Frame 1
Refresh
Idle
Low – MP operating in low-(normal) priority mode
High – MP operating in high-priority mode
STATUS[5:0]
10000 0
10000 1
10001 0
10001 1
10010 0
10010 1
10011 0
10011 1
10100 0
10100 1
10101 0
10101 1
10110 0
10110 1
10111 0
10111 1
11000 0
11000 1
11001 0
11001 1
11010 0
11010 1
11011 0
11011 1
11100 0
11100 1
11101 0
11101 1
11110 0
11110 1
11111 0
11111 1
CYCLE TYPE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Write Drain / SDRAM DCAB
68
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