SMJ320C80 Datasheet, PDF (69/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
address multiplexing
To support various RAM devices, the SMJ320C80 can provide multiplexed row and column addresses on its
address bus. A full 32-bit address is always output at row time. The alignment of column addresses is configured
by the value input on the AS[2:0] pins at row time.
A Pins
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row Time
A Pins
AS [2:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
001 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x 2 1 0
010 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x 2 1 0
100 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x 2 1 0
011 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x 2 1 0
100 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x 2 1 0
110 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x 2 1 0
111 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x 2 1 0
Column Time
Figure 53. Address Multiplexing
dynamic bus sizing
The ’C80 supports data bus sizes of 8, 16, 32, or 64 bits. The value input on the BS[1:0] pins at row time
indicates the bus size of the addressed memory. This determines the maximum number of bytes which the ’C80
can transfer during each column access. If the number of bytes to be transferred exceeds the bus size, multiple
accesses are performed automatically to complete the transfer.
Table 31. Bus Size Selection
BS[1:0]
00
01
10
11
BUS SIZE
8 bits
16 bits
32 bits
64 bits
The selected bus size also determines which portion of the data bus is used for the transfer. For 64-bit memory,
the entire data bus is used. For 32-bit memory, D[31:0] are used in little-endian mode and D[63:32] are used
in big-endian mode. 16-bit buses use D[15:0] and D[63:48] and 8-bit buses use D[7:0] and D[63:56] for little-
and big-endian modes, respectively. The ’C80 always aligns data to the proper portion of the bus and activates
the appropriate CAS strobes to ensure that only valid bytes are transferred.
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