SMJ320C80 Datasheet, PDF (32/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 5. Long-Immediate and Three-Register Opcodes
3322 2222222211 1111111100000000 00
1098 7654321098 7654321098765432 10
trap – – – – E – – – – – 1 1 0 0 0 0 0 0 1 I – – – – – – –
IND TR
cmnd – – – – – – – – – – 1 1 0 0 0 0 0 1 0 I – – – – – – –
Source1
rdcr
Dest
–––––110000100 I –––––––
IND CR
swcr
Dest
Source
110000101 I –––––––
IND CR
brcr – – – – – – – – – – 1 1 0 0 0 0 1 1 0 I – – – – – – –
IND CR
shift.dz
Dest
Source
110001000 I i n
Endmask
Rotate
shift.dm
Dest
Source
110001001 I i n
Endmask
Rotate
shift.ds
Dest
Source
110001010 I i n
Endmask
Rotate
shift.ez
Dest
Source
110001011 I i n
Endmask
Rotate
shift.em
Dest
Source
110001100 I i n
Endmask
Rotate
shift.es
Dest
Source
110001101 I i n
Endmask
Rotate
shift.iz
Dest
Source
110001110 I i n
Endmask
Rotate
shift.im
Dest
Source
110001111 I i n
Endmask
Rotate
and.tt
Dest
Source2
110010001 I –––––––
Source1
and.tf
Dest
Source2
110010010 I –––––––
Source1
and.ft
Dest
Source2
110010100 I –––––––
Source1
xor
Dest
Source2
110010110 I –––––––
Source1
or.tt
Dest
Source2
110010111 I –––––––
Source1
and.ff
Dest
Source2
110011000 I –––––––
Source1
xnor
Dest
Source2
110011001 I –––––––
Source1
or.tf
Dest
Source2
110011011 I –––––––
Source1
or.ft
Dest
Source2
110011101 I –––––––
Source1
or.ff
Dest
Source2
110011110 I –––––––
Source1
ld
Dest
Base
1 1 0 1 0 0 M SZ I S D – – – – –
Offset
ld.u
Dest
Base
1 1 0 1 0 1 M SZ I S D – – – – –
Offset
st
Source
Base
1 1 0 1 1 0 M SZ I S D – – – – –
Offset
dcache – – – – F
Source2
1 1 0 1 1 1 M0 0 I 0 0 – – – – –
Source
bsr
Link
–––––11100000A I –––––––
Offset
jsr
Link
Base
11100010A I –––––––
Offset
bbz
BITNUM
Source
11100100A I –––––––
Target
bbo
BITNUM
Source
11100101A I –––––––
Target
bcnd
Cond
Source
11100110A I –––––––
Target
cmp
Dest
Source2
111010000 I –––––––
Source1
add
Dest
Source2
11101100U I –––––––
Source1
sub
Dest
Source2
11101101U I –––––––
Source1
– Reserved bit (code as 0)
D Direct external access bit
E Emulation trap bit
F Clear present flags
i Invert endmask
l
Long immediate
M Modify, write modified address back to register
n Rotate sense for shifting
S Scale offset by data size
SZ Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword
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