SMJ320C80 Datasheet, PDF (121/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles
The SVRAM read- and write-transfer cycles transfer data between the SVRAM memory-array and the serial
register (SAM). The SMJ320C80 supports both normal and split transfers for SVRAMs. Read- and split-read
transfers resemble a standard read cycle. Write- and split-write transfers resemble a standard write cycle.
Because the ’C80’s TRG output is used as CAS, external logic must generate a TRG signal (by decoding
STATUS) to enable the SVRAM transfer cycle. The value output on A[31:0] at column time represents the SAM
tap point.
State
Col Pipe
r1
r2
r3
r5
r6
col
col
r1
c1
c2
c3
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
000
Cycle Type
PAC
DCAB
RL
A[31:0]
Row
Tap Pt.
RAS
CAS/DQM[7:0]
DSF
0 For Full, 1 For Split
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
ACTV
RTR
DCAB
Figure 98. SVRAM Burst-Length 1, 2-Cycle Latency Read-Transfer Cycle Timing
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